Recently, devices utilizing CCDs, such as analog memories, solid state imaging elements and delay lines, have been extensively developed. In the device construction thereof, it is the most important theme on design to incorporate CCDs having multiple stages on a relatively small chip. Particularly, a construction of a so-called parallel/serial conversion part which receives the charges transferred as input in parallel and outputs the same in serial raises a problem for high density integration.
However, in order to solve these problems in construction, a device in which a plurality of serial transfer CCDs are provided to relax the pitch interval, thereby resulting in a high density integration is proposed.
FIGS. 20(a) and 20(b) show a plan view and a cross-sectional view of CCD in a case where such construction is adopted in a solid state imaging element of an interline transfer system, disclosed in such as Japanese Patent Publication No. Sho. 53-35437 or "A 2 Million Pixel FIT-CCD Image Sensor for HDTV Camera System", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 214-215, February 1990.
In such a solid state imaging element, generally a serial transfer CCD is called as a horizontal CCD and a parallel transfer CCD is called as a vertical CCD. Therefore, these terms are used in the following description and the kind of CCD is a buried channel type.
In the conventional construction of FIG. 20(a), reference numeral 1 designates a photodiode arranged in a two-dimensional array. A transfer gate 2 for transferring the charges from the photodiode 1 to the vertical CCD channel 3 serving as a vertical channel is provided between the photodiode 1 and the vertical CCD channel 3. A final electrode 4 of the vertical CCD channel 3 is provided perpendicular to the vertical CCD channel 3 and is connected to the terminal .phi.VL. Here, although a transfer electrode is provided for the transfer by the vertical CCD channel 3 besides the final electrode 4, it is not illustrated in the figure for simplification.
A horizontal CCD channel 5 serving as a first horizontal CCD channel is provided in connection with the vertical CCD channel 3. A horizontal CCD channel 6 serving as a second horizontal channel is provided in parallel with the first horizontal CCD channel 5. Reference numerals 7 to 10 designate transfer electrodes for transfer by the horizontal CCDs. The electrodes 7 and 8 are connected to a terminal H1 and the electrodes 9 and 10 are connected to a terminal H2. The potential wells below the electrodes 8 and 10 are shallower than those of the electrodes 7 and 9. These horizontal CCD channels 5 and 6 constitute a so-called two-phase driving system CCD.
A control gate 11 for controlling the charge transfer from the horizontal CCD channel 5 to the horizontal CCD channel 6 is connected to a terminal HT. Reference numeral 15 designates a transfer channel of a layer below the control gate electrode 11.
In the solid-state imaging element of FIG. 20(a), charges transferred from the vertical CCD channel 3 are transferred column by column to the respective horizontal CCD channels 5 and 6, and then the pitch interval P.sub.c of the horizontal CCD is matched with the pixel pitch interval P.sub.x, in detail, P.sub.C =2P.sub.X, whereby the reduction in the pitch interval of horizontal CCD accompanying the increase in the pixel number is relaxed.
Next, a description is given of the operation of transferring the charges in the solid-state imaging element of FIG. 20(a) with reference to FIGS. 21 and 22.
FIGS. 21(a) to 21(d) show time charts of a clock pulse applied to each terminal in the construction of FIG. 20 for transferring charges. Pulses shown in FIGS. 21(a) to 21(d) are applied to each terminal .phi.VL, H1, HT and H2.
FIG. 22(a) is a cross-sectional view taken along a line XII--XII of FIG. 20(b) the change of potential at times t.sub.1 to t.sub.5 is schematically shown in FIG. 22(b) to 22(f) and the transition of signal charges (shown by slash lines), and FIG. 22(a) shows electrodes 4, 9, 11 and 7 and terminals .phi.VL, H2, HT and H1.
A description is given of the operation.
First of all, at time t.sub.1, clock pulses applied to respective terminals .phi.VL, H1 and H2 become all "H" level and charges are transferred from the vertical CCD channel 3 to opposite the electrodes 7 and 9 of the horizontal CCD channel 5. These respective charges are separated in the horizontal CCD channel 5 because of the potential barrier produced by the electrodes 8 and 10. Successively, at time t.sub.2, the terminal HT becomes "H" level and the charges transferred to below the electrode 9 of the horizontal CCD channel 5 are transferred to the transfer channel 15 below the control gate electrode 11. Furthermore, at time t.sub.3, the terminals H.sub.1 and H.sub.2 become "L" level and the charges are held in the transfer channel 15 below the control gate electrode 11. Then, at time t.sub.4, the terminal H.sub.1 again becomes "H" level and the charges in the transfer channel 15 below the control gate electrode 11 are transferred to below the electrode 7 of the horizontal CCD channel 6, and the whole transfer is completed at time t.sub.5. Meanwhile, charges transferred to below the electrode 7 of the horizontal CCD channel 5 are kept there. In this way, in the construction of FIG. 20(a), the charges transferred from the vertical CCD channel 3 are transferred column by column into a potential well below the electrode 7 of the horizontal channels 5 and 6.
When the whole transfer is completed, the charges stored below the electrode 7 of the horizontal CCD channels 5 and 6 are transferred to the left direction in the horizontal CCD channels 5 and 6 by the two-phase clock signal applied to the electrode of the horizontal CCD channels 5 and 6 after t.sub.6 (refer to FIGS. 21(a)-21(d), and they are output from the output part (not shown).
The conventional charge coupled device is constituted as described above, and the process for producing the electrodes 7 to 11 of the charge coupled device shown in FIG. 20 is as described in the following.
First, the control gate electrode 11 is produced and thereafter electrodes 7 and 9 are produced. Subsequently, ion implantation for establishing potentials in the channel regions in the horizontal CCD channels 5 and 6 are performed self-alignedly with the electrodes 7 and 9. Thereafter, electrodes 8 and 10 are produced.
Accordingly, in the conventional construction of FIG. 20(a), the electrode construction is a three-layer electrode structure comprising the control gate electrode 11, electrodes 7 and 9, and electrodes 8 and 10. Therefore, in a region where the control gate electrode 11 and respective electrodes 7 to 10 cross at right angles, the step differences of these electrodes become large, resulting in a likelihood of defects such as cutting of respective electrodes or short-circuiting between electrodes. These defects have caused reduction in the production yield of CCDs with respect to the production of these electrodes 7 to 10.